A novel design of high-speed divide-by-3/4 counter for a dual-modulus prescaler

نویسندگان

  • Yi-Shing Shih
  • Jenn-Hwan Tarng
چکیده

A novel design for a high-speed divide-by-3/4 counter is presented. The proposed design reduces not only the critical path delay but also the feedback path delay, hence it can increase the operating speed. With this divide-by-3/4 counter, a divide-by-127/128 dualmodulus prescaler (DMP), implemented in 0.18μm CMOS technology, shows a maximum operating frequency of 7.0GHz with 2.4mW power consumption at 1.8V supply voltage, which has 25% speed improvement and still consumes less power as well compared to the recentlyreported one.

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عنوان ژورنال:
  • IEICE Electronic Express

دوره 3  شماره 

صفحات  -

تاریخ انتشار 2006